The present invention relates to associative processors and, more particularly, to a method of performing arithmetical operations such as addition and subtraction on numbers stored in the associative array of an associative processor.
An associative processor is a device for parallel processing of a large volume of data. FIG. 1 is a schematic illustration of an associative processor 10. The heart of associative processor 10 is an array 12 of content addressable memory (CAM) cells 14 arranged in rows 16 and columns 18. Associative processor 10 also includes four registers for controlling CAM cells 14: two tags registers 20a and 20b that include many tag register cells 22, a mask register 24 that includes many mask register cells 26, and a pattern register 28 that includes many pattern register cells 30. Each cell 14, 22, 26 or 30 is capable of storing one bit (0 or 1). Each tags register 20 is a part of a tags logic block 36 that communicates with each row 16 via a dedicated word enable line 32 and a dedicated match result line 34, with each tag register cell 22 being associated with a respective row 16 via word enable line 32, match result line 34 and a dedicated logic unit 38. Each mask register cell 26 and each pattern register cell 30 is associated with a respective column 18. For illustrational simplicity, only three rows 16, only one word enable line 32, only one match result line 34 and only two logic units 38 are shown in FIG. 1. Note that the two tag register cells 22 that are associated with the same row 16 share the same word enable line 32 and the same match result line 34. Typical arrays 12 include 8192 (213) rows 16. The array 12 illustrated in FIG. 1 includes 32 columns 18. More typically, array 12 includes 96 or more columns 18.
Each machine cycle of associative processor 10 is either a compare cycle or a write cycle. Correspondingly, in a single machine cycle of associative processor 10, each CAM cell 14 performs one and only one of two kinds of elementary operations, as directed by the contents of the corresponding cells 22, 26 or 30 of registers 20a, 20b, 24 and 28: either a compare operation or a write operation. For both kinds of elementary operations, columns 18 that are to be active are designated by the presence of xe2x80x9c1xe2x80x9d bits in the associated mask register cells 26. The contents of tag register cells 22 of one of tags logic blocks 36 are broadcast to the associated rows 16 as xe2x80x9cwrite enablexe2x80x9d signals by that tags logic block 36 via word enable lines 32, with rows 16 that receive a xe2x80x9c1xe2x80x9d bit being activated. In a compare cycle, each activated row 16 generates a xe2x80x9c1xe2x80x9d bit match signal on match result line 34 of that row 16. Each activated CAM cell 14 of that row 16 compares its contents with the contents of the cell 30 of pattern register 28 that is associated with the column 18 of that CAM cell 14. If the two contents are identical (both xe2x80x9c0xe2x80x9d bits or both xe2x80x9c1xe2x80x9d bits), that CAM cell 14 allows the match signal to pass. Otherwise, that CAM cell 14 blocks the match signal. As a result, if the contents of all the activated CAM cells 14 of a row 16 match the contents of corresponding cells 30 of pattern register 28, the match signal reaches tags logic blocks 36. In a write cycle, the contents of pattern register cells 30 associated with activated columns 18 are written to the activated CAM cells 14 of those columns 18.
In the example illustrated in FIG. 1, the fifth through eighth columns 18 from the right are activated by the presence of xe2x80x9c1xe2x80x9ds in the corresponding mask register cells 26. A binary xe2x80x9c4xe2x80x9d (0100) is stored in the corresponding pattern register cells 30. A compare cycle performed by associative processor 10 in this configuration tests activated rows 16 to see if a binary xe2x80x9c4xe2x80x9d is stored in their fifth through eighth CAM cells 14 from the right. A write cycle performed by associative processor 10 in this configuration writes binary xe2x80x9c4xe2x80x9d to the fifth through eighth CAM cells 14 from the right of activated rows 16.
Each logic unit 38 can be configured to perform, in a single machine cycle, one or more of several logical operations (AND, OR, NOT, XOR, identity) whose inputs are one or more of: the bit stored in the associated tag register cell 22, the bit stored in the corresponding tag register cell 22 in the other tags logic block 36, and, if the cycle is a compare cycle, the presence or absence of a match signal on match result line 34. The AND, OR and XOR operations are binary operations (two inputs). The NOT and identity operations are unary operations (one input). The presence of a match signal on match result line 34 is treated as a binary xe2x80x9c1xe2x80x9d. The absence of a match signal on match result line 34 is treated as a binary xe2x80x9c0xe2x80x9d. The result of the logical operation is a single bit that is stored in the associated tag register cell 22. In the simplest set of logical operations, in a compare cycle, the only input is the presence or absence of a match signal on match result line 34 and the sole logical operation is an identity operation. The result of this operation is the writing to the associated tag register cell 22 of the bit corresponding to the presence or absence of a match signal on match result line 34.
In summary, in both kinds of elementary operations, tags register 20a or 20b and mask register 24 provide activation signals and pattern register 28 provides reference bits. Then, in a compare cycle, array 12 provides input to compare with the reference bits and tags registers 20a and 20b receive output; and in a write cycle, array 12 receives output that is identical to one or more reference bits.
Tags logic blocks 36a and 36b also can broadcast xe2x80x9c1xe2x80x9ds to all rows 16, to activate all rows 16 regardless of the contents of tags registers 20.
An additional function of tags registers 20 is to provide communication between rows 16. For example, suppose that the results of a compare operation executed on rows 16 have been stored in tags register 20a, wherein every bit corresponds to a particular row 16. By shifting tags register 20a, the results of this compare operation are communicated from their source rows 16 to other, target rows 16. In a single tags shift operation the compare result of every source row 16 is communicated to a corresponding target row 16, the distance between any source row 16 and the corresponding target row 16 being the distance of the shift.
More information about associative processors may be found in U.S. Pat. No. 5,974,521, to Akerib, which is incorporated by reference for all purposes as if fully set forth herein.
A prior art method of adding a first set of Q binary numbers {a(q), q=1 . . . Q}, stored in a first set of columns 18, to another set of Q binary numbers {b(q), q=1 . . . Q}, stored in a second set of columns 18, and storing the resulting Q binary numbers {s(q), q=1 . . . Q} in a third set of columns 18, is taught by Daniel P. Sieworek et al. in Computer Structures: Principles and Examples, Chapter 21: xe2x80x9cA productive implementation of an associative array processor: STARAN 319xe2x80x9d, McGraw-Hill, N.Y. (1982), also available at the URL
http://www.ulib.org/webRoot/Books/Saving_Bell_Books/SBN%20Co mputer%20Strucutres/csp0336.htm.
Without loss of generality, all the input numbers {a(q)} and {b(q)} can be assumed to have the same number of bits, because any number that is shorter than the longest input number can be left-padded with xe2x80x9c0xe2x80x9d bits. For any particular index q, a(q) and b(q) are initially stored in the same row 16, in different sets of respective columns 18, and s(q) is to be stored in the same row 16, typically in its own set of columns 18, although either a(q) or b(q) can be partly or completely overwritten with s(q) because once a bit of s(q) is computed, the bits of a(q) and b(q) that contributed to that bit of s(q) are no longer needed.
FIG. 2 is a flow chart of the algorithm of Sieworek et al. The input numbers are assumed to be M bits long. The m-th bit of a number a, b or s is designated by a[m], b[m] or s[m]. xe2x80x9cxxe2x80x9d refers to a bit stored in the tag register cell 22 of tags register 20a that is associated with the row 16 that stores the numbers a, b and s. xe2x80x9cyxe2x80x9d refers to a bit stored in the tag register cell 22 of tags register 20b that is associated with the row 16 that stores the numbers a, b and s. The symbol xe2x80x9c:=xe2x80x9d means xe2x80x9creplacementxe2x80x9d, as in ALGOL. At each stage of the loop over the bit index m, the carry bits are stored in tags register 20b. 
The activities of array processor 10 in each of the blocks of FIG. 2 now will be described in detail.
In the initialization step (block 40), all tag register cells 22 are set to zero, for example by all logic units 38 performing the logical operation XOR with both inputs being whatever bits are initially in tag register cells 22. In addition, all pattern register cells 30 are set to xe2x80x9c1xe2x80x9d.
The first machine cycle in the loop over m (block 42) is a compare cycle. All mask register cells 26 are set to xe2x80x9c0xe2x80x9d except for the mask register cell 26 corresponding to the column 18 that stores bits a[m]. One of tags logic blocks 36 broadcasts xe2x80x9c1xe2x80x9ds to all rows 16. The resulting match signals indicate whether the respective bits a[m] are xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Each logic unit 38 of tags logic block 36a performs an AND operation whose two inputs are the bit corresponding to the match signal received via match result line 34 and the bit previously stored in the corresponding tag register cell 22 of tags register 20b. Each logic unit 38 of tags logic block 36a then performs an XOR operation whose two inputs are the result of the AND operation and the bit previously stored in the associated tag register cell 22 of tags register 20a. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20a. Meanwhile, each logic unit 38 of tags logic block 36b performs an XOR operation whose two inputs are the bit corresponding to the match signal received via match result line 34 and the bit previously stored in the associated tag register cell 22 of tags register 20b. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20b. 
The second machine cycle in the loop over m (block 44) is a compare cycle. All mask register cells 26 are set to xe2x80x9c0xe2x80x9d except for the mask register cell 26 corresponding to the column 18 that stores bits b[m]. One of tags logic blocks 36 broadcasts xe2x80x9c1xe2x80x9ds to all rows 16. The resulting match signals indicate whether the respective bits b[m] are xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d. Each logic unit 38 of tags logic block 36a performs an AND operation whose two inputs are the bit corresponding to the match signal received via match result line 34 and the bit previously stored in the corresponding tag register cell 22 of tags register 20b. Each logic unit 38 of tags logic block 36a then performs an XOR operation whose two inputs are the result of the AND operation and the bit previously stored in the associated tag register cell 22 of tags register 20a. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20a. Meanwhile, each logic unit 38 of tags logic block 36b performs an XOR operation whose two inputs are the bit corresponding to the match signal received via match result line 34 and the bit previously stored in the associated tag register cell 22 of tags register 20b. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20b. 
The third machine cycle in the loop over m (block 46) is a write cycle. All mask register cells 26 are set to xe2x80x9c0xe2x80x9d except for the mask register cell 26 corresponding to the column 18 that is to store bits s[m]. Tags logic block 36b broadcasts the contents of tag register cells 22 of tags register 20a to all rows 16, as write enable signals. This results in the contents of tag register cells 22 of tags register 20a being written to the column 18 that is to store bits s[m]. Meanwhile, each logic unit 38 of tags logic block 36a performs an XOR operation whose two inputs are the bit previously stored in the associated tag register cell 22 of tags register 20a and the bit previously stored in the corresponding tag register cell 22 of tags register 20b. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20a. 
The fourth machine cycle in the loop over m (block 48) may be either a compare cycle or a write cycle, because no data are exchanged between array 12 and tags registers 20 in this machine cycle. Each logic unit 38 of tags logic block 36a performs an XOR operation whose two inputs both are the bit previously stored in the associated tag register cell 22 of tags register 20a. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20a. Meanwhile, each logic unit 38 of tags logic block 36b performs an XOR operation whose two inputs are the bit previously stored in the corresponding tag register cell 22 of tags register 20a and the bit previously stored in the associated tag register cell 22 of tags register 20b. The result of this XOR operation is stored in the associated tag register cell 22 of tags register 20b. 
In block 50, the bit index m is incremented. In block 52, m is tested to see if all input bits have been processed. If there are more input bits to process, the algorithm returns to block 42. Otherwise, in block 54, all mask register cells 26 are set to xe2x80x9c0xe2x80x9d except for the mask register cell 26 corresponding to the column 18 that is to store the final carry bits, bits s[M+1]. Tags logic block 36b broadcasts the contents of tag register cells 22 of tags register 20a to all rows 16, as write enable signals. This results in the contents of tag register cells 22 of tags register 20a being written to the column 18 that is to store bits s[M+1].
Shain, in U.S. patent application Ser. No. 10/108,451, which is incorporated by reference for all purposes as if fully set forth herein, teaches improved algorithms for addition and subtraction using an associative processor. Unlike the algorithm of Sieworek et al., these algorithms require only three machine cycles per pair of input bits. Shain""s algorithms have certain other advantages over the algorithm of Sieworek et al., as explained in U.S. Pat. No. 10/108,451. Nevertheless, all known prior art algorithms require that the numbers being combined be stored initially in separate sets of columns 18. There are applications in which it would be desirable to store all the numbers involved in the same set of columns 18. For example, in image processing, it often is desirable to combine all pixels that are separated by a fixed distance. The present invention enables such a parallel image processing operation to be performed without storing all the pixel values twice in two different sets of columns 18.
According to the present invention, given Q binary numbers a(q), where q is an index between 1 and Q, all of the binary numbers having a common number M of bits indexed by an index m between 1 and M, there is provided a method of, for a positive integer P that is less than Q and for all values of q between 1 and P, combining a(q) with a(q+Qxe2x88x92P) to produce M combination bits, including the steps of: (a) providing an array processor that includes an array of content addressable memory (CAM) cells; (b) storing the binary numbers in respective consecutive rows of the array; (c) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and P: performing at least one first logical operation having a match signal corresponding to the m-th bit of a(q) as an input thereof, thereby producing a first output, and (d) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and P: performing at least one second logical operation having, as inputs thereof, a match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and the first output, thereby producing a second output.
According to the present invention, given Q binary numbers a(q), where q is an index between 1 and Q, all of the binary numbers having a common number M of bits indexed by an index m between 1 and M, there is provided a method of, for a positive integer P that is less than Q and for all values of q between 1 and P, adding a(q) to a(q+Qxe2x88x92P), including the steps of: (a) providing an array processor that includes an array of content addressable memory (CAM) cells; (b) storing the binary numbers in respective consecutive rows of the array; (c) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and P: (i) performing at least one first logical operation having, as inputs thereof, a match signal corresponding to the m-th bit of a(q) and a respective carry bit, thereby producing a first output, and (ii) performing at least one second logical operation having, as inputs thereof, the match signal corresponding to the m-th bit of a(q) and the respective carry bit, thereby producing a second output; and (d) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and Q: (i) performing at least one third logical operation having, as inputs thereof, a match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and the first output, thereby producing a third output, and (ii) performing at least one fourth logical operation having, as inputs thereof, the match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and the second output, thereby providing a fourth output.
According to the present invention, given Q binary numbers a(q), where q is an index between 1 and Q, all of the binary numbers having a common number M of bits indexed by an index m between 1 and M, there is provided a method of, for a positive integer P that is less than Q and for all values of q between 1 and P, subtracting a(q+Qxe2x88x92P) from a(q), including the steps of: (a) providing an array processor that includes an array of content addressable memory (CAM) cells; (b) storing the binary numbers in respective consecutive rows of the array; and (c) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and P: (i) performing at least one first logical operation having, as inputs thereof, a match signal corresponding to the m-th bit of a(q) and a respective carry bit, thereby producing a first output, and (ii) performing at least one second logical operation having, as inputs thereof, the match signal corresponding to the m-th bit of a(q) and the respective carry bit, thereby producing a second output; and (d) for each value of m between 1 and M: substantially simultaneously, for each value of q between 1 and Q: (i) performing at least one third logical operation having, as inputs thereof, a match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and the first output, thereby producing a third output, and (ii) performing at least one fourth logical operation having, as inputs thereof, the match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and the second output, thereby providing a fourth output.
The present invention is a method of in-place associative processor arithmetic. Given an ordered set of Q binary input numbers a(q), where q is an index that runs from 1 through Q, the numbers a(q) are stored, in order, in consecutive rows 16, one number a(q) per row 16. Without loss of generality, if the longest number a(q) has M bits, all the input numbers can be regarded as having a common number M of bits, because any number that is shorter than M bits can be left-padded with xe2x80x9c0xe2x80x9d bits; and all the numbers a(q) are stored in a common set of M adjacent columns 18. The present invention is a method of, for each of the first P less than Q numbers a(q), combining a(q) with a(q+Qxe2x88x92P) in-place. In other words, with the possible exception of carry bits left over at the end of the associative processor operations described herein, no output bits are ever stored in any of CAM cells 14 other than CAM cells 14 that are initially used to store the numbers a(q). Although the scope of the present invention includes any arithmetic combination of a(q) with a(q+Qxe2x88x92P), the focus herein is on addition and subtraction, i.e., obtaining the sum a(q)+a(q+Qxe2x88x92P) or the difference a(q)xe2x88x92a(q+Qxe2x88x92P). More specifically, the focus herein is on an in-place implementation of the improved algorithms of Shain.
Letting m be an index that runs from 1 to M to index the bits of the numbers a(q) from least significant (m=1) to most significant (m=M), the present invention operates on one column 18 at a time, starting from the column 18 that stores the least significant bits and ending with the column 18 that stores the most significant bits. For each value of m, and for each value of q between 1 and P, the inputs are a(q), a(q+Qxe2x88x92P), and a carry bit y, from the previous column 18, that is stored in the q-th tag register cell 22 of tags register 20b. (For the m=1 column 18, all carry bits y are initialized to 0.) In the first machine cycle, for each value of q between 1 and P, the q-th logic unit 38 of tags register 20a executes a set of one or more logical operations on a match signal corresponding to the m-th bit of a(q) and on y, and stores the output bit of those logical operations in the q-th tag register cell 22 of tags register 20a. Meanwhile, for each value of q between 1 and P, the q-th logic unit 38 of tags register 20b executes another set of one or more logical operations on the match signal corresponding to the m-th bit of a(q) and on y, and stores the output bit of those logical operations in the q-th tag register cell 22 of tags register 20b. Then both tags register 20a and tags register 20b are shifted by Qxe2x88x92P, so that, for each value of q between 1 and P, the bits previously stored in the q-th tag register cell 22 of tags registers 20a and 20b now are stored in the q+Qxe2x88x92P-th tag register cell 22 of tags registers 20a and 20b. In the second machine cycle, for each value of q between 1 and P, the q+Qxe2x88x92P-th logic unit 38 of tags register 20a executes yet another set of one or more logical operations on a match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and on the bit in the q+Qxe2x88x92P-th tag register cell 22 of tags register 20a, and stores the output bit of those logical operations in the q+Qxe2x88x92P-th tag register cell 22 of tags register 20a. Meanwhile, for each value of q between 1 and P, the q+Qxe2x88x92P-th logic unit 38 of tags register 20b executes still another set of one or more logical operations on the match signal corresponding to the m-th bit of a(q+Qxe2x88x92P) and on the bit in the q+Qxe2x88x92P-th tag register cell 22 of tags register 20b, and stores the output bit of those logical operations in the q+Qxe2x88x92P-th tag register cell 22 of tags register 20b. Then both tags register 20a and tags register 20b are shifted by P-Q, so that, for each value of q between 1 and P, the bits previously stored in the q+Qxe2x88x92P-th tag register cell 22 of tags registers 20a and 20b now are stored in the q-th tag register cell 22 of tags registers 20a and 20b. 
At this point, if the logical operations have been those of Shain""s improved algorithms, then, depending on the nature of the logical operations performed, the desired combination bits may be found either in tag register cells 22 of tags register 20a or in tag register cells 22 of tags register 20b. These bits now are written to the column 18 that is to receive the output of the combination of the m-th bits of a(q) and a(q+Qxe2x88x92P), for q=I through P. Preferably, for each value of q between 1 and P, the m-th bit of a(q) is replaced with the desired combination bit, to keep the processing within the original M columns 18 to the extent possible. This is allowed because the input bit that is being replaced is no longer needed.
In the accompanying claims, the set of one or more logical operations, that are executed by logic units 38 of tags register 20a in the first machine cycle, is called the xe2x80x9cfirstxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9cfirstxe2x80x9d output; and the set of one or more logical operations, that are executed by logic units 38 of tags register 20b in the second machine cycle, is called the xe2x80x9cfourthxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9cfourthxe2x80x9d output. In some of the claims, the set of one or more logical operations, that are executed by logic units 38 of tags register 20b in the first machine cycle, is called the xe2x80x9csecondxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9csecondxe2x80x9d output; and the set of one or more logical operations, that are executed by logic units 38 of tags register 20a in the second machine cycle, is called the xe2x80x9cthirdxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9cthirdxe2x80x9d output. In others of the claims, the set of one or more logical operations, that are executed by logic units 38 of tags register 20a in the second machine cycle, is called the xe2x80x9csecondxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9csecondxe2x80x9d output; and the set of one or more logical operations, that are executed by logic units 38 of tags register 20b in the first machine cycle, is called the xe2x80x9cthirdxe2x80x9d set of logical operations, with the output of that set of logical operations being called the xe2x80x9cthirdxe2x80x9d output. Nevertheless, each set of claims is internally self-consistent with regard to these two usages of xe2x80x9csecondxe2x80x9d and xe2x80x9cthirdxe2x80x9d, so that no confusion arises.
The present implementation of Shain""s algorithms retains their advantages over the prior art algorithm of Sieworek et al. Specifically:
1. As noted above, Shain""s algorithms include only three machine cycles per pair of input bits: two compare cycles and one write cycle.
2. In Shain""s algorithms, the bits x that are stored in tag register cells 22 of tags register 20a are neither initialized before the loop over m nor shared between successive iterations of the loop over m. Only the carry bits (y), that are stored in tag register cells 22 of tags register 20b, are initialized (to xe2x80x9c0xe2x80x9d) before the loop over m and shared between successive iterations of the loop over m.
3. Shain""s second addition algorithm includes only five logical operations (two ANDs, two XORs, one OR) per pair of input bits, vs. nine logical operations per pair of input bits in the algorithm of Sieworek et al. Similarly, Shain""s subtraction algorithm of the present invention includes only seven logical operations (two ANDs, two XORs, two NOTs, one OR) per pair of input bits, of which only five are binary logical operations.
4. In Shain""s second addition algorithm, for each value of q between 1 and P, only three of the logical operations include a(q+Qxe2x88x92P) as a direct or indirect argument, vs. six logical operations in the algorithm of Sieworek et al. Similarly, in Shain""s subtraction algorithm, for each value of q between 1 and P, only four of the logical operations include a(q+Qxe2x88x92P) as a direct or indirect argument.
5. Both Shain""s second addition algorithm and Shain""s subtraction algorithm include OR operations. The algorithm of Sieworek et al. lacks OR operations.
6. In both Shain""s second addition algorithm and Shain""s subtraction algorithm, there are only two XOR operations per pair of input bits, vs. seven XOR operations in Sieworek""s algorithm.
7. In both Shain""s second addition algorithm and Shain""s subtraction algorithm, only logic units 38 of tags logic block 36a perform XOR operations. It follows that only logic units 38 of tags logic blocks 36a need to be configured to do XOR operations. This leads to a simplification of associative processor 10, because the hardware needed to perform an XOR operation is more complicated than the hardware needed to perform the other logical operations.